The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. These advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down also presents critical challenges for manufacturing and processing IC devices. For example, group III-V semiconductor material based channel devices have been introduced that can provide improved device performance when compared to silicon based channel devices. However, achieving electrically passive interfaces between group III-V semiconductor materials and insulator materials (such as a gate dielectric layer) have proved difficult. Such interfaces typically exhibit electrically active defects that cause group III-V semiconductor material based channel devices to perform similarly, if not worse than, silicon based channel devices. Accordingly, although existing group III-V semiconductor material based channel devices and methods of manufacturing the same have been generally adequate for their intended purposes, as device scaling down continues, they have not been entirely satisfactory in all respects.